Hardware Engineering Diagnostic Index & Bench-Tested Field Manuals
ASUS • CODE Q-Code 55 Severity: High Verified Manual Indexed: 2026-10-23
ASUS

ASUS ROG Maximus Z790 Dark Hero Error Q-Code 55: DDR5 Memory Not Installed

Q-Code 55 denotes 'Memory not installed', indicating the memory controller (IMC) failed to detect or train DDR5 modules during initial Power-On Self-Test (POST). This typically stems from uneven CPU socket mounting pressure bending LGA1700 pins, marginal memory training timing under aggressive XMP/EXPO profiles on cold boot, or insufficient VDD/VDDQ/MC voltage rail supply.

Hardware Diagnostic Matrix

Spec Ref #4f473f0d
Severity Level High
Estimated Fix Time 20-40 Mins
Difficulty Grade Intermediate
Equipment Sector PC Hardware & Motherboards

Required Diagnostic Tools & Instrumentation

Torx T8/Precision Phillips #2 Screwdriver (Hand tool)
Torque Screwdriver (0.6 Nm rated) (Hand tool)
High-magnification Jeweler Loupe or USB Microscope (Diagnostic tool)
99% Isopropyl Alcohol and Lint-Free Microfiber Swabs (Cleaning tool)

Multimeter Probing Targets & Circuit Tolerances

Bench Calibrated ±5%
Test Point / Circuit Target Nominal Spec Expected State Fault Condition
Main Logic DC Bus 3.3V / 5.0V DC (±0.1V) Stable DC Potential <2.9V (Brownout / Sag)
Thermistor / NTC Sensor 10kΩ - 100kΩ @ 25°C Smooth Thermal Curve 0Ω (Short) or ∞ (Open)
Safety Ground / PE Continuity < 0.5Ω Resistance Solid Earth Bond > 1.0Ω (Floating Chassis)

Common Symptoms & Fault Manifestations

  • Motherboard halts on 2-digit debug LED displaying '55' during POST
  • System fails to post from a completely powered-down cold start, but may reboot successfully once warm
  • Yellow/Orange DRAM Q-LED remains continuously illuminated

Root Causes & System Failure Modes

Failure Mechanism #01

Uneven CPU cooler torque deflecting the LGA1700 socket substrate and losing contact on DDR5 memory channel pins

Failure Mechanism #02

Marginal IMC (Integrated Memory Controller) VDD_IMC/VCCSA voltage or DDR5 PMIC voltage (VDD/VDDQ < 1.35V) failing aggressive XMP cold-boot training algorithms

Failure Mechanism #03

Micro-debris, flux residue, or unseated DIMM pins in slot A2/B2 preventing proper SPD handshake on the SMBus

High-Voltage & Mechanical Safety Isolation

Prior to opening access panels, disconnecting terminals, or probing wiring, perform complete lock-out / tag-out (LOTO). Disconnect all AC mains, DC string isolators, and lithium battery banks. Allow internal smoothing capacitors at least 3 to 5 minutes to dissipate stored residual energy below safe threshold (<30VDC).

Step-by-Step Diagnostic & Resolution Procedure

1

Clear CMOS and Single DIMM Fallback

Switch off PSU and disconnect AC power. Press and hold the Rear I/O Clear CMOS button for 10 seconds. Remove the stick in DIMM_A2, leaving a single stick in DIMM_B2 to bypass dual-channel training routines, and verify if default JEDEC speeds (4800-5600 MT/s) successfully post.

2

CPU Socket & Contact Inspection

Remove the CPU cooler and CPU. Inspect the LGA1700 pin grid with a jeweler's loupe for bent, bridging, or recessed pins—specifically along the outer quadrants responsible for DDR5 traces. Reinstall the CPU using an aftermarket contact frame or cross-pattern tightening torqued evenly to 0.6 Nm to prevent uneven socket deflection.

3

DIMM Slot Decontamination & Reseating

Clean DDR5 gold edge fingers with 99% IPA. Blow clean compressed air into slots DIMM_A2 and DIMM_B2 to dislodge manufacturing debris. Insert the modules with firm, even downward force until both latch mechanisms click fully into place.

4

UEFI Firmware Flash & Cold Boot IMC Voltage Tuning

Update UEFI BIOS using ASUS USB BIOS Flashback to the latest AGESA/Microcode release. Enter UEFI, enable XMP I/II, and manually configure CPU VDDQ TX to 1.30V–1.35V, CPU VDD2 (Memory Controller) to 1.30V–1.35V, and DRAM VDD/VDDQ to 1.40V. Enable 'Memory Fast Boot' to disabled/auto to ensure complete cold boot training.

Hardware Reset & Fault Clear Sequence

Controller Procedure
$ Disconnect AC power, hold the rear Clear CMOS button for 10 seconds, then hold the front panel power switch for 15 seconds to discharge residual capacitance before powering on.

Prevention & Routine Maintenance Guidelines

  • Always populate primary DDR5 slots A2 and B2 first for signal trace termination integrity.
  • Avoid over-torquing cooler mounting brackets on LGA1700 platforms; consider using an LGA1700 contact frame.

Frequently Asked Diagnostic Questions

What does error code Q-Code 55 indicate on ASUS ROG Maximus Z790 Dark Hero?

Q-Code 55 denotes 'Memory not installed', indicating the memory controller (IMC) failed to detect or train DDR5 modules during initial Power-On Self-Test (POST). This typically stems from uneven CPU socket mounting pressure bending LGA1700 pins, marginal memory training timing under aggressive XMP/EXPO profiles on cold boot, or insufficient VDD/VDDQ/MC voltage rail supply. In engineering telemetry, it indicates ddr5 memory not installed requiring circuit verification.

What are the primary triggers causing error Q-Code 55?

Diagnostic bench telemetry isolates the following common root causes: Uneven CPU cooler torque deflecting the LGA1700 socket substrate and losing contact on DDR5 memory channel pins; Marginal IMC (Integrated Memory Controller) VDD_IMC/VCCSA voltage or DDR5 PMIC voltage (VDD/VDDQ < 1.35V) failing aggressive XMP cold-boot training algorithms; Micro-debris, flux residue, or unseated DIMM pins in slot A2/B2 preventing proper SPD handshake on the SMBus.

How do I reset and clear ASUS error Q-Code 55?

Disconnect AC power, hold the rear Clear CMOS button for 10 seconds, then hold the front panel power switch for 15 seconds to discharge residual capacitance before powering on. If the error status repeats immediately after clearing, discontinue clearing and test circuit continuity.

Can I safely resolve error Q-Code 55 without specialized shop tooling?

This fault is graded as Intermediate difficulty with High severity. Standard diagnostics require an insulated digital multimeter and appropriate hand tools. Always observe high-voltage isolation procedures.